The 4th. MARC symposium took place in the Hasso Plattner Institute at University of Potsdam, in Germany.  I anticipate that most of the submissions to MARC symposia in the near future will be about work on the Xeon Phi (the commercial product based on the MIC architecture); in this occasion, all presentations were related to the Single-chip Cloud Computer (SCC).

Although I could not attend the first day of the event due to schedule conflicts, I managed to make it for the second day (barely on time for my presentation) and went through the proceedings afterwards.  In summary, plenty of proof was given (as in previous symposia) that both distributed shared memory and message passing programming models can be supported on SCC-like systems.  The runtime systems and library stacks are not necessarily stable enough for production environments, but a lot has been learned from the efforts of the MARC, about the viability of non-coherent systems for the future.  In that sense, I consider the MARC symposia a success for Intel and all researchers involved, and I look forward to future interesting and sometimes unusual solutions presented there.

My presentation at the MARC was about the improved communication protocol for message passing that was developed at Intel for the RCKMPI2 library.  The aim of the first protocol, released with RCKMPI, was to eliminate the overhead related to TCP/IP on the SCC; this was achieved by communicating through the on die SRAM directly, effectively bypassing the TCP/IP stack.  In the second iteration, the efficiency of message passing for larger MPI jobs was significantly improved, and the design was made flexible enough to allow the use of the Message Passing Buffer (MPB) for multiple types of communication: MPI collectives, MPI point-to-point, process management and inter-core signaling.  In our submission, we talk about the changes and how MPI-2 dynamic processes (basically MPI_Comm_spawn) were supported.  Support for dynamic processes was required for our work on the invasive programming model, presented in the ARCS 2012 conference.

The ARCS conference was a bit larger event than the MARC symposium.  A lot of topics were discussed; as expected, my attention was caught mostly by presentations about future many-core programming models and observed trends.  In particular, the keynote by Sebastian Steibl from Intel Labs, got most of my attention.  He discussed recent developments from researchers at Intel, that resulted in a very low power IA32 core.  What is interesting is that to achieve this low power operation, near threshold voltage (NTV) circuit design was used for the cores.  I had read about it before in The Register and Anandtech websites, from their 2012′s International Solid-State Circuits Conference (ISSCC) coverage.  What I had not considered was that threshold voltage is quite sensible to variations related to the manufacturing process.  The consequence is that even in what could be considered a homogeneous many-core architecture, in order to operate at maximum efficiency, the chip may need to be handled as a heterogeneous architecture due to the varying frequencies at which each core reaches its peak efficiency.  Imagine a 256 core CPU with clusters of cores that operate at different frequencies.  Utilizing such a CPU efficiently with today’s programming models will be challenging, to say the least.

As mentioned earlier, our contribution to the ARCS conference was in relation to the InvasIC protect, in this case with MPI on the SCC.  We went to great length to reduce the latency of process management operations for the SCC, so that applications can re-adjust their process counts at runtime with as low as possible overhead.